This invention relates generally to the fabrication of integrated circuits and more particularly to a borderless contact structure and its method of manufacture.
In memory device structures, decreased cell size is a goal in order to obtain better performance and to permit more cells per chip. One constraint in decreasing memory cell size relates to the formation of electrical contacts to the device areas where lithographic overlay tolerances must be allowed in order to avoid shorting between the contacts and adjacent structures, For example, in an FET memory cell the spacing between the gate electrodes of adjacent cells and the diffused region must allow for the inability to precisely align a contact mask with the device areas in order to open contact holes through an insulating layer. A border 10 is required around contact area 11, as illustrated in FIG. 1, to assure the separation of the contact from the edges 12 of gate electrodes or word lines 13 and the edges 14 of field oxide regions 15. The edges 17 of electrodes 16 are also illustrated which are vertically separated from lines 13 by a dielectric layer. Border 10, having a width of about 1.5 microns, for example, represents wasted chip surface area. Processes have been devised to permit smaller emitter base spacing in bipolar devices, for example, U.S. Pat. No. 4,160,991 in which a polysilicon layer is used to contact the base area. The polysilicon layer is separated from a metal emitter contact layer by an insulating layer. The polysilicon layer overlays the field oxide and a metal contact to the polysilicon layer is formed through the insulating layer. U.S. Pat. No. 4,157,269 also concerns a process to permit smaller emitter base spacing in which contact to a polysilicon layer is made which is remote from the device regions.
We have now found a process which provides for borderless contacts for FET cells resulting in decreased cell size and performance advantages.